1. Field of the Invention
The present invention relates to integrated circuit devices and, in particular, to an improved vertical punch-through cell.
2. Discussion of the Prior Art
Vertical charge-coupled-device (CCD) or vertical punch-through cells become a cost-effective solution to memory design when further downscaling of MOSFETs is prevented by fundamental design and fabrication limitations. Neither vertical CCD nor vertical punch-through cells require transistors. Thus, these devices permit the development of higher density DRAMs without the need for downscaling of transistors.
FIGS. 1A and 1B illustrate a conventional vertical CCD cell. As best shown in FIG. 1B, a typical vertical CCD cell consists of a buried column 10 which is formed at the interface between a silicon substrate 12 and an overlying epitaxial silicon layer 14. A row line 16 is separated from the epitaxial layer 14 by a thin layer of dielectric material 18.
This designs suffers from several disadvantages. First, in a folded bit line configuration, wide spaces are required between the cells to avoid charge coupling between the CCD cell and the adjacent reference column. Second, the amount of stored charge in the conventional CCD cell is sensitive to threshold voltages. Third, the conventional cell is sensitive to surface defects over the gate dielectric area. Fourth, the conventional CCD device is sensitive to the type of gate dielectric material used.